/*
 * Copyright (c) 2020 Xilinx Inc.
 * Written by Francisco Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#ifndef __ACE_MST_REGS_H__
#define __ACE_MST_REGS_H__

#define BRIDGE_IDENTIFICATION_REG_ADDR		0x0
#define LAST_BRIDGE_REG_ADDR			0x4
#define VERSION_REG_ADDR			0x20
#define BRIDGE_TYPE_REG_ADDR			0x24
#define MODE_SELECT_REG_ADDR			0x38
#define RESET_REG_ADDR				0x3C

#define RD_REQ_FIFO_PUSH_DESC_REG_ADDR		0x300
#define RD_REQ_FIFO_FREE_LEVEL_REG_ADDR		0x304
#define RD_REQ_INTR_COMP_STATUS_REG_ADDR	0x308
#define RD_REQ_INTR_COMP_CLEAR_REG_ADDR		0x30C
#define RD_REQ_INTR_COMP_ENABLE_REG_ADDR	0x310

#define RD_RESP_FREE_DESC_REG_ADDR		0x314
#define RD_RESP_FIFO_POP_DESC_REG_ADDR		0x318
#define RD_RESP_FIFO_FILL_LEVEL_REG_ADDR	0x31C

#define WR_REQ_FIFO_PUSH_DESC_REG_ADDR		0x320
#define WR_REQ_FIFO_FREE_LEVEL_REG_ADDR		0x324
#define WR_REQ_INTR_COMP_STATUS_REG_ADDR	0x328
#define WR_REQ_INTR_COMP_CLEAR_REG_ADDR		0x32C
#define WR_REQ_INTR_COMP_ENABLE_REG_ADDR	0x330

#define WR_RESP_FREE_DESC_REG_ADDR		0x334
#define WR_RESP_FIFO_POP_DESC_REG_ADDR		0x338
#define WR_RESP_FIFO_FILL_LEVEL_REG_ADDR	0x33C

#define SN_REQ_FREE_DESC_REG_ADDR		0x340
#define SN_REQ_FIFO_POP_DESC_REG_ADDR		0x344
#define SN_REQ_FIFO_FILL_LEVEL_REG_ADDR		0x348

#define SN_RESP_FIFO_PUSH_DESC_REG_ADDR		0x34C
#define SN_RESP_FIFO_FREE_LEVEL_REG_ADDR	0x350
#define SN_RESP_INTR_COMP_STATUS_REG_ADDR	0x354
#define SN_RESP_INTR_COMP_CLEAR_REG_ADDR	0x358
#define SN_RESP_INTR_COMP_ENABLE_REG_ADDR	0x35C

#define SN_DATA_FIFO_PUSH_DESC_REG_ADDR		0x360
#define SN_DATA_FIFO_FREE_LEVEL_REG_ADDR	0x364
#define SN_DATA_INTR_COMP_STATUS_REG_ADDR	0x368
#define SN_DATA_INTR_COMP_CLEAR_REG_ADDR	0x36C
#define SN_DATA_INTR_COMP_ENABLE_REG_ADDR	0x370

#define ACE_MST_INTR_FIFO_ENABLE_REG_ADDR	0x374

#define RD_REQ_DESC_N_TXN_TYPE_REG_ADDR		0x0
#define RD_REQ_DESC_N_SIZE_REG_ADDR		0x4
#define RD_REQ_DESC_N_AXSIZE_REG_ADDR		0x8
#define RD_REQ_DESC_N_ATTR_REG_ADDR		0xC
#define RD_REQ_DESC_N_AXADDR_0_REG_ADDR		0x10
#define RD_REQ_DESC_N_AXADDR_1_REG_ADDR		0x14
#define RD_REQ_DESC_N_AXID_0_REG_ADDR		0x20

#define RD_RESP_DESC_N_DATA_OFFSET_REG_ADDR	0x0
#define RD_RESP_DESC_N_DATA_SIZE_REG_ADDR	0x4
#define RD_RESP_DESC_N_RESP_REG_ADDR		0x18
#define RD_RESP_DESC_N_XID_0_REG_ADDR		0x1C

#define WR_REQ_DESC_N_TXN_TYPE_REG_ADDR		0x0
#define WR_REQ_DESC_N_SIZE_REG_ADDR		0x4
#define WR_REQ_DESC_N_DATA_OFFSET_REG_ADDR	0x8
#define WR_REQ_DESC_N_AXSIZE_REG_ADDR		0x2C
#define WR_REQ_DESC_N_ATTR_REG_ADDR		0x30
#define WR_REQ_DESC_N_AXADDR_0_REG_ADDR		0x34
#define WR_REQ_DESC_N_AXADDR_1_REG_ADDR		0x38
#define WR_REQ_DESC_N_AXID_0_REG_ADDR		0x44

#define WR_RESP_DESC_N_RESP_REG_ADDR		0x0
#define WR_RESP_DESC_N_XID_0_REG_ADDR		0x4

#define SN_REQ_DESC_N_ATTR_REG_ADDR		0x0
#define SN_REQ_DESC_N_ACADDR_0_REG_ADDR		0x4
#define SN_REQ_DESC_N_ACADDR_1_REG_ADDR		0x8
#define SN_RESP_DESC_N_RESP_REG_ADDR 		0x0

#define RD_REQ_DESC_N_BASE_ADDR			0x3000
#define RD_RESP_DESC_N_BASE_ADDR		0x4000
#define WR_REQ_DESC_N_BASE_ADDR			0x5000
#define WR_RESP_DESC_N_BASE_ADDR		0x6000
#define SN_REQ_DESC_N_BASE_ADDR			0x7000
#define SN_RESP_DESC_N_BASE_ADDR		0x7200

#define RD_DATA_RAM				0x8000
#define WR_DATA_RAM				0xc000
#define WSTRB_DATA_RAM				0x10000
#define CD_DATA_RAM				0x14000

#endif
